128k x 8 static ram cy7c1009v33 cy7c109v33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 september 3, 1999 features ? high speed ?t aa = 15, 20, 25ns v cc = 3.3v 10% low active power ? 432 mw (max.) ? 288 mw (l version) low cmos standby power ? 18 mw (max.) ? 7.2 mw (l version) 2.0v data retention automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce 1 , ce 2 , and oe options functional description the cy7c109v33/cy7c1009v33 is a high-performance cmos static ram organized as 131,072 words by 8 bits. easy memory expansion is provided by an active low chip enable (ce 1 ), an active high chip enable (ce 2 ), an active low out- put enable (oe ), and three-state drivers. writing to the device is accomplished by taking chip enable one (ce 1 ) and write enable (we ) inputs low and chip enable two (ce 2 ) input high. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 16 ). reading from the device is accomplished by taking chip en- able one (ce 1 ) and output enable (oe ) low while forcing write enable (we ) and chip enable two (ce 2 ) high. under these conditions, the contents of the memory location speci- fied by the address pins will ap pear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 high or ce 2 low), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high, and we low). the cy7c109v33 is available in standard 32-pin, 400-mil-wide soj package. the cy7c1009v33 is available in a 32-pin, 300-mil-wide soj package. the cy7c1009v33 and cy7c109v33 are functionally equivalent in all other respects. shaded areas contain preliminary information. selection guide 7c109v33-12 7c1009v33-12 7c109v33-15 7c1009v33-15 7c109v33-20 7c1009v33-20 7c109v33-25 7c1009v33-25 maximum access time (ns) 12 15 20 20 maximum operating current (ma) 130 120 110 110 maximum operating current (ma) low power version 90 80 70 70 maximum cmos standby current (ma) standard 5555 maximum cmos standby current (ma) low power version 2222 14 15 logic block diagram pin configurations a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe i/o 0 ce 2 i/o 1 i/o 2 i/o 3 512 x 256 x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 11 a 13 a 12 a a 10 ce 1 a a 16 a 9 1 2 3 4 5 6 7 8 9 10 11 14 19 20 24 23 22 21 25 28 27 26 top view soj 12 13 29 32 31 30 16 15 17 18 gnd a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 we v cc a 15 a 13 a 8 a 9 i/o 7 i/o 6 i/o 5 i/o 4 109v33?1 a 2 nc i/o 0 i/o 1 i/o 2 ce 1 oe a 10 i/o 3 a 1 a 0 a 11 ce 2 109v33?2 a 6 a 7 a 16 a 14 a 12 we v cc a 4 a 13 a 8 a 9 oe tsop i top view (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 i/o 2 i/o 1 gnd i/o 7 i/o 4 i/o 5 i/o 6 i/o 0 ce a 11 a 5 17 18 8 9 10 11 12 13 14 15 16 ce 2 a 15 nc a 10 i/o 3 a 1 a 0 a 3 a 2 109v33?3
cy7c1009v33 cy7c109v33 2 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage on v cc to relative gnd [1] .... ? 0.5v to +7.0v dc voltage applied to outputs in high z state [1] ..................................... ? 0.5v to v cc +0.5v dc input voltage [1] ................................. ? 0.5v to v cc +0.5v current into outputs (low)......................................... 20 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 3.3v 300mv electrical characteristics over the operating range test conditions 7c109v33-12 7c1009v33-12 7c1009v33-15 7c109v33 ? 15 parameter description min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.3 0.8 ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 1 +1 ? 1+1 a i oz output leakage current gnd < v i < v cc , output disabled ? 5 +5 ? 5+5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 130 120 ma l 90 80 i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce 1 > v ih or ce 2 < v il , v in > v ih or v in < v il , f = f max 25 20 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce 1 > v cc ? 0.3v, or ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f=0 55ma l 22 shaded areas contain preliminary information. notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. t a is the case temperature.
cy7c1009v33 cy7c109v33 3 electrical characteristics over the operating range (continued) test conditions 7c1009v33-20 7c109v33-20 7c1009v33-25 7c109v33-25 parameter description min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.3 0.8 ? 0.3 0.8 v i ix input load current gnd < v i < v cc ? 1+1 ? 1+1 a i oz output leakage current gnd < v i < v cc , output disabled ? 5+5 ? 5+5 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 110 110 ma l70 70 i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce 1 > v ih or ce 2 < v il , v in > v ih or v in < v il , f = f max 20 20 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce 1 > v cc ? 0.3v, or ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f=0 55ma l2 2 capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 6pf c out output capacitance 8 pf note: 3. tested initially and after any design or process changes that may affect these parameters. ac test loads and waveforms 109v33 ? 4 109v33 ? 5 90% 10% 3.0v gnd 90% 10% all input pulses 3v output 30 pf including jig and scope 3v output 5 pf including jig and scope (a) (b) 3ns 3 ns output r1 480 ? r1 480 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th
cy7c1009v33 cy7c109v33 4 switching characteristics [4] over the operating range 7c1009v33-12 7c109v33-12 7c1009v33-15 7c109v33-15 7c1009v33-20 7c109v33-20 7c1009v33-25 7c109v33-25 parameter description min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 12 15 20 20 ns t aa address to data valid 12 15 20 20 ns t oha data hold from address change 3 333ns t ace ce 1 low to data valid, ce 2 high to data valid 12 15 20 20 ns t doe oe low to data valid 6788ns t lzoe oe low to low z 0 000ns t hzoe oe high to high z [5, 6] 6788ns t lzce ce 1 low to low z, ce 2 high to low z [6] 3 333ns t hzce ce 1 high to high z, ce 2 low to high z [5, 6] 6788ns t pu ce 1 low to power-up, ce 2 high to power-up 0 000ns t pd ce 1 high to power-down, ce 2 low to power-down 12 15 20 20 ns write cycle [7,8] t wc write cycle time 12 15 20 20 ns t sce ce 1 low to write end, ce 2 high to write end 10 12 15 15 ns t aw address set-up to write end 10 12 15 15 ns t ha address hold from write end 0 000ns t sa address set-up to write start 0 000ns t pwe we pulse width 10 12 15 15 ns t sd data set-up to write end 7 81010ns t hd data hold from write end 0 000ns t lzwe we high to low z [6] 3 333ns t hzwe we low to high z [5, 6] 6788ns shaded areas contain preliminary information. data retention characteristics over the operating range (l version only) parameter description conditions min. max unit v dr v cc for data retention no input may exceed v cc + 0.5v v cc = v dr = 2.0v, ce 1 > v cc ? 0.3v or ce 2 < 0.3v, v in > v cc ? 0.3v or v in < 0.3v 2.0 v i ccdr data retention current 200 a t cdr chip deselect to data retention time 0 ns t r operation recovery time t rc ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 high, and we low. ce 1 and we must be low and ce 2 high to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1009v33 cy7c109v33 5 switching waveforms read cycle no. 1 [9, 10] read cycle no. 2 (oe controlled) [10, 11] write cycle no. 1 (ce 1 or ce 2 controlled) [12, 13] notes: 9. device is continuously selected. oe , ce 1 = v il , ce 2 = v ih . 10. we is high for read cycle. 11. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. 12. data i/o is high impedance if oe = v ih . 13. if ce 1 goes high or ce 2 goes low simultaneously with we going high, the output remains in a high-impedance state. previous data valid data valid t rc t aa t oha 109v33 ? 6 address data out 109v33 ? 7 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 icc isb impedance address ce 2 data out v cc supply current 109v33 ? 8 t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce 1 address ce 2 we data i/o
cy7c1009v33 cy7c109v33 6 write cycle no. 2 (we controlled, oe high during write) [12, 13] write cycle no. 3 (we controlled, oe low) [13] note: 14. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) 109v33 ? 9 t hd t sd t pwe t sa t ha t aw t sce t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 14 109v33 ? 10 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t sce t wc t hzwe ce 1 address ce 2 we data i/o note 14
cy7c1009v33 cy7c109v33 7 document #: 38 ? 00635 ? a truth table ce 1 ce 2 oe we i/o 0 ? i/o 7 mode power h x x x high z power-down standby (i sb ) x l x x high z power-down standby (i sb ) l h l h data out read active (i cc ) l h x l data in write active (i cc ) l h h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 12 cy7c109v33-12vc v33 32-lead (400-mil) molded soj commercial cy7c1009v33-12vc v32 32-lead (300-mil) molded soj cy7c1009v33l-12vc v32 32-lead (300-mil) molded soj cy7c109v33-12zc z32 32-lead tsop type i 15 cy7c109v33 ? 15vc v33 32-lead (400-mil) molded soj commercial cy7c1009v33-15vc v32 32-lead (300-mil) molded soj cy7c1009v33l-15vc v32 32-lead (300-mil) molded soj cy7c109v33-15zc z32 32-lead tsop type i 20 cy7c109v33 ? 20vc v33 32-lead (400-mil) molded soj commercial cy7c109v33 ? 20zc z32 32-lead tsop type i cy7c109v33l ? 20vc v33 32-lead (400-mil) molded soj cy7c109v33l ? 20zc z32 32-lead tsop type i cy7c1009v33-20vc v32 32-lead (300-mil) molded soj cy7c1009v33l-20vc v32 32-lead (300-mil) molded soj 25 cy7c109v33 ? 25vc v33 32-lead (400-mil) molded soj commercial cy7c109v33l ? 25vc v33 32-lead (400-mil) molded soj cy7c109v33l ? 25zc z32 32-lead tsop type i cy7c1009v33l-25vc v32 32-lead (300-mil) molded soj cy7c1009v33-25vc v32 32-lead (300-mil) molded soj shaded areas contain preliminary information.
cy7c1009v33 cy7c109v33 8 package diagrams 32-lead (300-mil) molded soj v32 51-85041-a 32-lead (400-mil) molded soj v33 51-85033-a
cy7c1009v33 cy7c109v33 ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams (continued) 51-85056-b 32-lead thin small outline package z32
|
